This Ph.D is a Professor of Electrical and Computer Engineering and the Director of the Analog Alliance and the Microelectronics Systems Laboratory at a major University.  He directs the University Cadence Design Kit, and co-directs Spice to IBIS activity. His teaching and research focuses on VLSI, ASICs, interconnect structures building microsystems and nanosystems.  He is also an IEEE Fellow.

• Application Specific Processors and Microsystems. ASICs, SOCs and SOPs.  This topic includes the following projects:
• Integrated sub-system design for networking, radar, and other applications.
• Networking Hardware, including routing and Network Security.
• Low-power chip design.
• Hardware for Speech Recognition.
• SOI chip design, including rad-hard design.
• IC Design flows and CAD.
• Nanocomputing and nano-enabled structures for nanoelectronics.
• Molecular Computing.
• III-V circuit design and applications.
• Interconnect Structures and Circuits. High-density, high-speed and low-power on-chip and intra-chip interconnect circuits and structures.  Applications that benefit from high bandwidth interconnect and SOP design techniques. This topic includes the following projects:
• High-speed transceiver design, including SERDES.
• Design of High density packaging.
• Signal and Power integrity.
• AC Coupled Interconnect
• On-chip interconnect
• 3D IC's and Packaging
• Nanointerconnect fabrication and design.
• Chip-Package Codesign, including IBIS.
• Computer-Aided Design of Interconnect structures.

• Ph. D., Electrical and Electronic Engineering
• B.S., Electrical and Electronic Engineering; First Class Honors
• B.S., Physics and Mathematics

Expert Witness Services;

• Expert Witness Reports
• Intellectual Property
• Patent Analysis 
• Patent Litigation
• Technical Consultant