This expert witness has participated in the IEEE standardization of Verilog and SystemVerilog, and has extensively used Verilog for design and verification.  He has been actively involved in the Verilog 1364 standardization as a member of the Behavioral Task Force since 1997.  This Task Force was responsible for the synthesis and verification enhancements to the language.  He was also a member of the IEEE 1364.1 Verilog RTL Synthesis Interoperability Working Group, and of the Accellera SystemVerilog Working Group, which is adding further enhancements to the Verilog language for synthesis and verification.

He has authored conference papers on verification for the Synopsys Users Group ( "SNUG" ) and DVCon.  He has also instructed Introduction and Advanced Verilog for Synthesis and Verification courses.

• ASIC Design
• ASIC Verification
• Language Standards
• SystemVerilog
• Verilog

• MBA
• BS Electrical Engineering

Expert Witness Services:

• Deposition
• Patent Litigation
• Technical Consultant